In fabricating microelectronic semiconductor devices and the like on a semiconductor wafer (substrate or chip), e.g., of silicon, to form an integrated circuit (IC), etc., various metal layers and insulation layers are deposited in selective sequence, and in some cases oxide layers are grown in situ on the wafer. To maximize integration of device components in the available wafer area to fit more components in the same area, increased IC miniaturization is utilized Reduced pitch dimensions are needed for denser packing of components per present day very large scale integration (VLSI), e.g., at sub-micron (below 1 micron, i.e., 1,000 nanometer or 10,000 angstrom) dimensions.
A typical conventional oxide layer formation process used in the IC fabrication of a semiconductor wafer involves a one-step thermal oxidation of a surface thereof in an oxidation furnace, e.g., of quartz. The wafer, e.g., at room temperature, i.e., about 20.degree. C., is loaded, e.g., progressively, via a boat containing a row of successive wafers, into the furnace which is maintained at a low loading temperature, e.g., of about 400-600.degree. C., and the temperature of the furnace is "ramped up", i.e., increased, along with the temperature of the wafer, to a high oxidizing temperature, e.g., of about 700-1200.degree. C. The wafer surface is then subjected to oxidation to grow in situ the oxide layer thereon. After the oxide layer is so grown, the furnace temperature is "ramped down", i.e., decreased, to a low unloading temperature, e.g., of about 400-600.degree. C., and the wafer is unloaded from the furnace for further processing.
In general, the oxidation furnace is operated 24 hours a day, and never cools down to room temperature. Instead, the furnace varies from a low loading or unloading temperature, e.g., of about 400-600.degree. C., to a high oxidizing temperature, e.g., of about 700-1200.degree. C. Hence, during the loading of the row of room temperature wafers into the furnace, the leading wafer is exposed to the heating conditions in the furnace significantly earlier than the trailing wafer, whereas the trailing wafer is correspondingly exposed to the exterior ambient air significantly longer than the leading wafer.
In particular, silicon dioxide (SiO.sub.2) is in most cases grown in situ as a high temperature stable insulating oxide on silicon. The oxide thickness uniformity within a given wafer and from wafer to wafer, as well as the reproducibility, i.e., from run to run, of the desired target thickness is of great importance for modern semiconductor circuits with small design ground rules and small oxide thicknesses.
One major problem is to control significantly the interim time between a typically contemplated wafer precleaning step, e.g., chemical precleaning by etching with buffered HF solution, and the beginning of the in situ thermal oxidation. During this interim time, a native oxide grows in situ on the silicon wafer at room temperature followed by a low temperature oxide which grows during loading and during ramp up to the high oxidizing temperature.
The last processing step before the deposition of a thermal oxide, i.e., before the thermal oxidation for growing the oxide in situ, is usually a wafer precleaning step, as noted above. During this precleaning step, the previously grown native oxide, which forms on mere contact with air at room temperature, i.e., about 20.degree. C., is removed. Unfortunately, after the precleaning step, a new oxide layer starts growing on the silicon wafer as a native oxide at room temperature unless the precleaning step is performed in an inert atmosphere, i.e., under an inert ambient such as nitrogen, argon, or other inactive gas, and also as a low temperature oxide unless the wafer is loaded into the oxidation furnace without coming into contact with ambient air.
The thickness of the new oxide layer grown at room temperature depends mainly on the duration between the precleaning step and the incorporation, i.e., progressive loading, of the wafer into the oxidation furnace. In practice, this time is difficult to control in a fabrication environment. This is mainly because the leading wafer in the row of wafers being loaded into the furnace is exposed to the heating conditions in the furnace significantly earlier than the trailing wafer, whereas the trailing wafer is correspondingly exposed to the exterior ambient air significantly longer than the leading wafer. As a result, the oxide layer which is produced by the usual one-step thermal oxidation process is non-uniform in thickness and extent, and thus non-homogeneous in character.
It is desirable to have a process providing improved thickness uniformity of a thin oxide layer in semiconductor wafer fabrication, within the given wafer and from wafer to wafer, with reproducibility from run to run of the desired target thickness, which creates more ideal or uniform starting conditions for the thermal oxidation of the wafer surface so as to render less important or inconsequential any uncontrolled formation of an oxide layer during the interim time between a wafer precleaning step and the beginning of the thermal oxidation.